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.TH "IONIC_DV_PD_SET_SQCMB" "3" "2025-06-23" "ionic" "Ionic Programmer\[cq]s Manual"
.hy
.SH NAME
.PP
ionic_dv_pd_set_sqcmb - Specify send queue preference for controller
memory bar
.SH SYNOPSIS
.IP
.nf
\f[C]
#include <infiniband/ionic_dv.h>

int ionic_dv_pd_set_sqcmb(struct ibv_pd *ibpd, bool enable, bool expdb,
                           bool require);
\f[R]
.fi
.SH DESCRIPTION
.PP
\f[B]ionic_dv_pd_set_sqcmb()\f[R] configures the controller memory bar
(CMB) preferences for send queues created under the protection domain
\f[I]ibpd\f[R].
Send queues created after this call will use the CMB according to the
specified preferences.
.PP
When CMB is enabled, the send queue ring buffer is placed in device
memory (the controller memory bar) instead of host memory, which can
reduce doorbell latency.
.PP
Express doorbell (expdb) is an additional optimization that further
reduces doorbell overhead when the send queue is placed in CMB.
.PP
The \f[I]require\f[R] flag controls whether creation should fail if the
requested CMB preferences cannot be met.
When \f[I]require\f[R] is false, the driver will fall back to host
memory if CMB is unavailable.
.SH ARGUMENTS
.TP
\f[I]ibpd\f[R]
The protection domain to configure.
Must be an ionic protection domain.
.TP
\f[I]enable\f[R]
Allow the use of the controller memory bar for send queues.
.TP
\f[I]expdb\f[R]
Allow the use of express doorbell optimizations.
Only meaningful when \f[I]enable\f[R] is true.
.TP
\f[I]require\f[R]
Require that the CMB preferences are met.
If true and the preferences cannot be satisfied, queue creation will
fail instead of falling back to host memory.
Only meaningful when \f[I]enable\f[R] is true.
.SH RETURN VALUE
.PP
Returns 0 on success, or a positive errno value on failure:
.TP
\f[I]EPERM\f[R]
\f[I]ibpd\f[R] is not an ionic protection domain.
.TP
\f[I]EINVAL\f[R]
\f[I]require\f[R] is true with \f[I]expdb\f[R] true, but the device does
not support express doorbell for send queues.
.SH SEE ALSO
.PP
\f[B]ionicdv\f[R](7), \f[B]ionic_dv_pd_set_rqcmb\f[R](3),
\f[B]ionic_dv_pd_set_udma_mask\f[R](3)
.SH AUTHORS
.PP
Advanced Micro Devices, Inc.
